`include "ascon_define.v"

module `RX_BUF_2_32B_64
    (
    input                                        clk_i,
    input                                        rstn_i,

    input                                        en_i,
    input                                        wen_i,
    input                  [`AHB_BUS_ADDR_W-1:0] waddr_i,
    input                  [`AHB_BUS_DATA_W-1:0] wdata_i,

    input                      [`BUF_ADDR_W-1:0] raddr_i,
    output                            [`M_W-1:0] rdata_o
    );

reg                                              wen_0  , wen_1  ;
reg                                              en_0  , en_1  ;
wire                       [`AHB_BUS_DATA_W-1:0] wdata_0, wdata_1;
wire                       [`AHB_BUS_DATA_W-1:0] rdata_0, rdata_1;

wire                                       [0:0] wByte_sel;
wire                           [`BUF_ADDR_W-1:0] waddr;

wire                           [`BUF_ADDR_W-1:0] raddr;

assign waddr            = waddr_i[3+`BUF_ADDR_W-1:3];
assign wByte_sel        = waddr_i[2:2];

assign raddr            = raddr_i;

always@(*)
begin : WEN_X_PROG
  case (wByte_sel)
    1'b0 : begin
      wen_0             = wen_i;
      wen_1             = 1'b0;
    end
    1'b1 : begin
      wen_0             = 1'b0;
      wen_1             = wen_i;
    end
    default: begin
      wen_0             = wen_i;
      wen_1             = wen_i;
    end
  endcase
end

always@(*)
begin : EN_X_PROG
  case (wByte_sel)
    1'b0 : begin
      en_0              = en_i;
      en_1              = 1'b0;
    end
    1'b1 : begin
      en_0              = 1'b0;
      en_1              = en_i;
    end
    default: begin
      en_0              = en_i;
      en_1              = en_i;
    end
  endcase
end

// 小端存储
assign wdata_0          = wdata_i;
assign wdata_1          = wdata_i;

// 输出读数据选通

assign rdata_o          = {rdata_1,rdata_0};

// 第一字
`RAM_32B_64
u_ram_0(
    .clk_i                             (clk_i                                  ),
    .rstn_i                            (rstn_i                                 ),

    .en_i                              (en_0                                   ),
    .wen_i                             (wen_0                                  ),
    .waddr_i                           (waddr                                  ),
    .wdata_i                           (wdata_0                                ),

    .raddr_i                           (raddr                                  ),
    .rdata_o                           (rdata_0                                )
);

// 第二字
`RAM_32B_64
u_ram_1
(
    .clk_i                             (clk_i                                  ),
    .rstn_i                            (rstn_i                                 ),

    .en_i                              (en_1                                   ),
    .wen_i                             (wen_1                                  ),
    .waddr_i                           (waddr                                  ),
    .wdata_i                           (wdata_1                                ),

    .raddr_i                           (raddr                                  ),
    .rdata_o                           (rdata_1                                )
);

endmodule